Development of a novel deep silicon tapered via etch process for through-silicon interconnection in 3-D integrated systems

被引：14

作者：

Nagarajan, Ranganathan ^{[1
]}

Ebin, Liao ^{[1
]}

Dayong, Lee ^{[2
]}

Seng, Soh Chee ^{[2
]}

Prasad, Krishnamachar ^{[2
]}

Balasubramanian, N. ^{[1
]}

机构：

[1] Inst Microelect, 11 Sci Pk Rd,Singapore Sci Pk 2, Singapore 117685, Singapore

[2] Nanyang Technol Univ, Sch Elect & Elect Engn, Div Microelect, Singapore 639798, Singapore

来源：

56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/ECTC.2006.1645674

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A novel dual etch process technology has been demonstrated which provides an opportunity to precisely and independently control the etch throughput and required via slope that is required to achieve conformal deposition of dielectric, copper diffusion barrier and copper seed metallization. It is further shown how a void-free copper via plating has been achieved for implementation into 3-D integrated systems.

引用

页码：383 / +

页数：2

共 11 条

[1]

BHARDWAJ J, 1997, ANN M EL SOC MONTR Q

[2] Balancing the etching and passivation in time-multiplexed deep dry etching of silicon [J].

Blaw, MA ;

Zijlstra, T ;

van der Drift, E .

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2001, 19 (06) :2930-2934

[3] 2.5-Dimensional VLSI system integration [J].

Deng, YD ;

Maly, WP .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2005, 13 (06) :668-677

[4]

FRYE RC, 1992, MULT CHIP MOD C 1992, P155

[5]

JOYCE H, 2004, IEEE T ELECTRON DEV, V51, P1765

[6] Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection [J].

Knickerbocker, JU ;

Andry, PS ;

Buchwalter, LP ;

Deutsch, A ;

Horton, RR ;

Jenkins, KA ;

Kwark, YH ;

McVicker, G ;

Patel, CS ;

Polastre, RJ ;

Schuster, C ;

Sharma, A ;

Sri-Jayantha, SM ;

Surovic, CW ;

Tsang, CK ;

Webb, BC ;

Wright, SL ;

McKnight, SR ;

Sprogis, EJ ;

Dang, B .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2005, 49 (4-5) :725-753

[7] Through-wafer copper electroplating for three-dimensional interconnects [J].

Nguyen, NT ;

Boellaard, E ;

Pham, NP ;

Kutchoukov, VG ;

Craciun, G ;

Sarro, PM .

JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2002, 12 (04) :395-399

[8]

Ranganathan N, 2005, ELEC COMP C, P343

[9]

REIF R, 2002, INT S QUAL EL DES IS

[10] IC stacking technology using fine pitch, nanoscale through silicon vias [J].

Spiesshoefer, S ;

Schaper, L .

53RD ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2003 PROCEEDINGS, 2003, :631-633

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