A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

被引:7
|
作者
Kuo, Ko-Chi [1 ]
Wu, Chi-Wei [1 ]
机构
[1] Natl Sun Yat Sen Univ, Dept Comp Sci & Engn, Kaohsiung 80424, Taiwan
关键词
Noise filtering; Switched biasing; Voltage-Controlled Oscillator (VCO); Phase Locked Loop (PLL); Charge pump; Phase frequency detector (PFD); Frequency divider; PHASE-NOISE; TUNING RANGE; CMOS; OSCILLATOR; DESIGN; FEEDBACK; REDUCTION; DIVIDER; PLL;
D O I
10.1016/j.eswa.2013.07.087
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22 GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is -121.6 dBc/Hz at 1 MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1 mW. The chip with an area of 1.048 x 1.076 mm(2) is fabricated in a TSMC 0.18 mu m CMOS 1P6M technology process. (C) 2013 Elsevier Ltd. All rights reserved.
引用
收藏
页码:622 / 634
页数:13
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