6T SRAM Design for Wide Voltage Range in 28nm FDSOI

被引：0
|
作者：
Thomas, O. [1 ,2 ]
Zimmer, B. [2 ]
Pelloux-Prayer, B. [3 ]
Planes, N. [3 ]
Akyel, K-C. [3 ]
Ciampolini, L. [3 ]
Flatresse, P.
Nikolic, B. [2 ,3 ]
机构：
[1] CEA LETI MINATEC Campus Grenoble, Grenoble, France
[2] Univ Calif Berkeley, BWRC, Berkeley, CA USA
[3] STMicroelectron Crolles, Crolles, France
来源：
IEEE INTERNATIONAL SOI CONFERENCE | 2012年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Unique features of the 28nm ultra-thin body and buried oxide (UTBB) FDSOI technology enable the operation of SRAM in a wide voltage range. Minimum operating voltage limitations of a high-density (HD) 6-transistor (6T) SRAM can be overcome by using a single p-well (SPW) bitcell design in FDSOI. Transient simulations of dynamic failure metrics suggest that a HD 6T SPW array with 128 cells per bitline operates down to 0.65V in typical conditions with no assist techniques. In addition, a wide back-bias voltage range enables run-time tradeoffs between the low leakage current in the sleep mode and the short access time in the active mode, making it attractive for high-performance portable applications.
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页数：2
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