Supply Voltage Minimization Techniques for SRAM Leakage Reduction

In low power design, it is difficult to suppress leakage current. In memory, leakage power reduction during data-retention in SRAM standby is often addressed by reducing the supply voltage. Each SRAM cell has a minimum supply voltage parameter called the data-retention voltage (DRV), above which the stored bit can be retained reliably. As supply voltage is lowered, leakage power reduces. This paper models the DRV of SRAM module, and analyzes the SRAM cell stability when V-DD approaches DRV. DRV of the 4 KB SRAM module in a 0.13 mm technology ranges between 60 and 390 mv.