共 50 条
- [21] Design of Miniaturized UWB Low Noise Amplifier Based on 65 nm CMOS Technology 2021 PHOTONICS & ELECTROMAGNETICS RESEARCH SYMPOSIUM (PIERS 2021), 2021, : 482 - 487
- [22] Radiation Tolerant, Low Noise Phase Locked Loops in 65 nm CMOS Technology ADVANCEMENTS IN NUCLEAR INSTRUMENTATION MEASUREMENT METHODS AND THEIR APPLICATIONS (ANIMMA 2017), 2018, 170
- [25] Mitigation of TSV-Substrate Noise Coupling in 3-D CMOS SOI Technology 2013 IEEE 22ND CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS), 2013, : 73 - 76
- [26] Low-Power and High-Frequency Ring Oscillator Design in 65nm CMOS Technology 2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2017, : 533 - 536
- [27] FD-SOI material enabling CMOS technology disruption from 65nm to 12nm and beyond 2017 IEEE INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT), 2017,
- [28] Employing 65 nm CMOS SOI for 60 GHz WPAN applications 2008 IEEE INTERNATIONAL CONFERENCE ON MICROWAVES, COMMUNICATIONS, ANTENNAS AND ELECTRONIC SYSTEMS, 2008, : 342 - +
- [30] A 2.4 GHz CMOS Ultra Low Power Low Noise Amplifler Design with 65 nm CMOS Technology 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 1480 - 1483