A 5.6 ppm/°C Temperature Coefficient, 87-dB PSRR, Sub-1-V Voltage Reference in 65-nm CMOS Exploiting the Zero-Temperature-Coefficient Point

被引：76
作者：
Jiang, Jize [1 ]
Shu, Wei [1 ]
Chang, Joseph S. [1 ]
机构：
[1] Nanyang Technol Univ, Singapore, Singapore
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2017年 / 52卷 / 03期
关键词：
Curvature compensation; high-precision; MOSFET-only; sub-1-V; system-on-chip; voltage reference; wide-band high power supply rejection ratio (PSRR); zero-temperature coefficient (ZTC) point; BANDGAP REFERENCE; INACCURACY; CIRCUITS; 3-SIGMA; SENSOR;
D O I：
10.1109/JSSC.2016.2627544
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes an MOSFET-only voltage reference realized in 65-nm CMOS featuring a temperature coefficient (TC) of 5.6 ppm/degrees C from -40 degrees C to 125 degrees C, a power supply rejection ratio of 87 dB from dc up to 800 kHz (and 75 dB at 1 MHz), a minimum supply voltage of 0.8 V, and a power dissipation of 13 mu W. These attributes are achieved by exploiting the zero-TC point of an MOSFET and combining it with a novel curvature-compensation technique, an active attenuator, and an impedance-adapting frequency compensation scheme.
引用
收藏
页码：623 / 633
页数：11
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