FPGA Based Frequency Synthesizer for 14-Band MB-OFDM UWB Transceivers

The design of the All Digital Receiver circuit in this paper uses Delay Locked Loop (DLL) as the main core as a replacement for of PLL. A 14 -band CMOS frequency synthesizer using DLL is designed for spur reduction in MB-OFDM UWB system. DLL reduces the design complexity since the main difference when considering with PLL is there is no internal voltage control oscillator. The feedback more specific sub harmonics are obtained from SSB mixer for 14 band generation. This DLL based frequency synthesizer reduces the interference and provides efficient signal with negligible bit error rate. The proposed frequency synthesizer provides 0.620jenergy consumption, 210Ps delay, 18Gbps data rate, 210mwstatic power.