A Tool for VLIW Processors Code Optimizing

被引：0
|
作者：
Mego, Roman [1 ]
Fryza, Tomas [1 ]
机构：
[1] Brno Univ Technol, Dept Radio Elect, Brno, Czech Republic
来源：
PROCEEDINGS OF 2018 13TH INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING AND SYSTEMS (ICCES) | 2018年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
The paper demonstrates the behavior of low- and high-level programming languages on the multicore digital signal processors based on Very Long Instruction Word architecture. The aim of the paper is to present a tool that can be used to implement any digital signal processing algorithm on such processors with efficiency of the low-level languages, but with the advantages of the high-level programming languages. Preliminary result is the software that uses a signal-flow graph approach to describe an algorithm, generates low-level assembly code and provides (graphical) information about the algorithm.
引用
收藏
页码：601 / 604
页数：4
相关论文
共 50 条
  • [31] Optimal subgraph covering for customisable VLIW processors
    Lue, Y. -S.
    Shen, L.
    Huang, L. -B.
    Wang, Z. -Y.
    Xiao, N.
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2009, 3 (01): : 14 - 23
  • [32] Datapath and ISA customization for soft VLIW processors
    Saghir, Mazen A. R.
    El-Majzoub, Mohamad
    Akl, Patrick
    RECONFIG 2006: PROCEEDINGS OF THE 2006 IEEE INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGA'S, 2006, : 280 - +
  • [33] Code positioning for VLIW architectures
    Cilio, AGM
    Corporaal, H
    HIGH-PERFORMANCE COMPUTING AND NETWORKING, 2001, 2110 : 332 - 343
  • [34] A distributed control path architecture for VLIW processors
    Zhong, HT
    Fan, K
    Mahlke, S
    Schlansker, M
    PACT 2005: 14TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, 2005, : 197 - 206
  • [35] Evaluation of speed and area of clustered VLIW processors
    Terechko, A
    Garg, M
    Corporaal, H
    18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS, 2005, : 557 - 563
  • [36] Fast Simulation of Systems Embedding VLIW Processors
    Michel, Luc
    Fournel, Nicolas
    Petrot, Frederic
    CODES+ISSS'12:PROCEEDINGS OF THE TENTH ACM INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE-CODESIGN AND SYSTEM SYNTHESIS, 2012, : 143 - 149
  • [37] Power Estimation Methodology for VLIW Digital Signal Processors
    Ibrahim, Mostafa E. A.
    Rupp, Markus
    Fahmy, Hossam A. H.
    2008 42ND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, VOLS 1-4, 2008, : 1840 - +
  • [38] Compiler supports for VLIW DSP processors with SIMD intrinsics
    Kuan, Chi-Bang
    Lee, Jenq Kuen
    CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2012, 24 (05): : 517 - 532
  • [39] VLIW across multiple superscalar processors on a single chip
    Kim, SP
    Hoare, RR
    Dietz, HG
    1997 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, 1997, : 166 - 175
  • [40] Multithreaded extension to multicluster VLIW processors for embedded applications
    Barretta, D
    Fornaciari, W
    Sami, M
    Bagni, D
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, : 748 - 749
12345