A sub-1-V, high precision, ultra low-power, process trimmable, resistorless voltage reference with low cost 90-nm standard CMOS technology

被引：6

作者：

Samir, Anass ^{[1
]}

Kussener, Edith ^{[2
]}

Rahajandraibe, Wenceslas ^{[2
]}

Girardeau, Ludovic ^{[1
]}

Bert, Yannick ^{[1
]}

Barthelemy, Herve ^{[2
]}

机构：

[1] STMicroelectronics, ZI Rousset Peynier, F-13106 Rousset, France

[2] Univ Provence, Microelect Dept, Inst Mat Microelect & Nanosci, IM2NP,UMR CNRS 6242, Toulon, France

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2012年 / 73卷 / 03期

关键词：

CMOS voltage reference; Ultra low-power; Weak inversion; Sub-threshold; Process variation; Process trimming management; Temperature compensation; REFERENCE CIRCUIT; PPM/DEGREES-C;

D O I：

10.1007/s10470-012-9852-5

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A low power voltage reference generator operating with a supply voltage ranging from 1.6 to 3.6 V has been implemented in a 90-nm standard CMOS technology. The reference is based on MOSFETs that are biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6 V and at 125A degrees C is 173 nA. It provides a 771 mV voltage reference. A temperature coefficient of 7.5 ppm/A degrees C is achieved at best and 39.5 ppm/A degrees C on average, in a range from -40 to 125A degrees C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. Several process parameters affect the performance of the proposed voltage reference circuit, so a process adjustment aimed at correcting errors in the reference voltage caused by these variations is dealt with. The total block area is 0.03 mm(2).

引用

页码：693 / 706

页数：14

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