Design of High Speed Dynamic Comparator in 28nm CMOS

被引：0
|
作者：
Cao, Yuan [1 ]
Zhang, Chunming [1 ]
机构：
[1] Xian Univ Posts & Telecommun, Shaanxi Prov Res Ctr Telecommun ASIC Design, Xian, Shaanxi, Peoples R China
来源：
CONFERENCE PROCEEDINGS OF 2018 IEEE ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIMEASIA 2018) | 2018年
关键词：
high speed dynamic comparator; 28nm CMOS process; low power supply voltage;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a high-speed dynamic comparator which could optimize the basically differential amplifier and class AB latch circuit, designed and verified in UMC 28nm CMOS process with Cadence IC615. The proposed design is powered by 1.05V supply and the output signal only exhibits 0.2mV/0.8mV offset voltage, 63ps/44ps delay respectively when the clock signal at the 5/10 GHz. The proposed circuit is useful for the electronic industries, high-speed ADCs and SerDes.
引用
收藏
页码：1 / 4
页数：4
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