Novel forksheet device architecture as ultimate logic scaling device towards 2nm

被引：58

作者：

Weckx, P. ^{[1
]}

Ryckaert, J. ^{[1
]}

Litta, E. Dentoni ^{[1
]}

Yakimets, D. ^{[1
]}

Matagne, P. ^{[1
]}

Schuddinck, P. ^{[1
]}

Jang, D. ^{[1
]}

Chehab, B. ^{[1
]}

Baert, R. ^{[1
]}

Gupta, M. ^{[1
]}

Oniki, Y. ^{[1
]}

Ragnarsson, L. -A. ^{[1
]}

Horiguchi, N. ^{[1
]}

Spessot, A. ^{[1
]}

Verkest, D. ^{[1
]}

机构：

[1] IMEC, Leuven, Belgium

来源：

2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2019年

关键词：

D O I：

10.1109/iedm19573.2019.8993635

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

To compensate for expected gate pitch scaling slowdown below 42nm, several scaling boosters are needed to reduce the logic standard cell height (CH). However, limited scaling benefits can be achieved using FinFET and Gate all around (GAA) nanosheets (NSHs) due integration limits in achieving tight PMOS to NMOS (PN) separation. Therefore, a novel forksheet (FSH) device architecture is proposed achieving extremely scaled PN space using limited additional processing complexity. The FSH achieves 10% frequency increase at iso-power and 24% power reduction at iso-frequency compared to GAA nanosheet with a combined area scaling of 20%. SRAM bit cell area scaling of 30% and read delay performance increase is shown.

引用

页数：4