Design of Low Power High Speed Full Adder Cell with XOR/XNOR Logic Gates

被引：0

作者：

Alluri, Sudhakar ^{[1
]}

Dasharatha, M. ^{[1
]}

Naik, B. Rajendra ^{[1
]}

Reddy, N. S. S. ^{[2
]}

机构：

[1] Osmania Univ, Elect & Commun Engn Dept, Hyderabad, Telangana State, India

[2] Osmania Univ, Elect & Commun Engn Dept, VCE, Hyderabad, Telangana State, India

来源：

2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND SIGNAL PROCESSING (ICCSP), VOL. 1 | 2016年

关键词：

CMOS; full adder; exclusive-NOR (XNOR); low power; delay; VLSI; High-Level synthesis; CMOS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This present paper, a 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 180 nm technology. The proposed results are compared with the previous existing designs in terms of power and delay. It is observed that the power consumption is reduced by 65.19 % for three transistor XNOR gate and 48.11% for eight transistor full adder. It is also observed that the delay is reduced by 31.82% for three transistors XNOR gate and 28.76% for eight transistors full adder.

引用

页码：565 / 570

页数：6

共 50 条

[1] Low Power High Speed Full Adder Cell with XOR/XNOR Logic Gates in 90nmTechnology
Manikannan, G.
Mahendran, K.
Prabakaran, P.
2017 INTERNATIONAL CONFERENCE ON TECHNICAL ADVANCEMENTS IN COMPUTERS AND COMMUNICATIONS (ICTACC), 2017, : 61 - 65
[2] Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
Naseri, Hamed
Timarchi, Somayeh
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26 (08) : 1481 - 1493
[3] Design of Swing Dependent XOR-XNOR Gates based Hybrid Full Adder
Malini, P.
Balaji, G. Naveen
Boopathiraja, K.
Gautami, A.
Shanmugavadivu, P.
Pandian, S. Chenthur
2019 5TH INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING & COMMUNICATION SYSTEMS (ICACCS), 2019, : 1164 - 1170
[4] A high-speed and scalable XOR-XNOR-based hybrid full adder design
Hasan, Mehedi
Hussain, Md. Shahbaz
Hossain, Mainul
Hasan, Mohd.
Zaman, Hasan U.
Islam, Sharnali
COMPUTERS & ELECTRICAL ENGINEERING, 2021, 93
[5] A high-speed and scalable XOR-XNOR-based hybrid full adder design
Hasan, Mehedi
Hussain, Md. Shahbaz
Hossain, Mainul
Hasan, Mohd.
Zaman, Hasan U.
Islam, Sharnali
Computers and Electrical Engineering, 2021, 93
[6] New XOR/XNOR and full adder circuits for low voltage, low power applications
Lee, H
Sobelman, GE
MICROELECTRONICS JOURNAL, 1998, 29 (08) : 509 - 517
[7] Design of New Low-Power High-Performance Full Adder with New XOR-XNOR Circuit
Morad, Milad Jalalian Abbas
Talebiyan, Seyyed Reza
Pakniyat, Ebrahim
SECOND INTERNATIONAL CONGRESS ON TECHNOLOGY, COMMUNICATION AND KNOWLEDGE (ICTCK 2015), 2015, : 153 - 158
[8] High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR-XNOR Cell
Kandpal, Jyoti
Tomar, Abhishek
Agarwal, Mayur
Sharma, K. K.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2020, 28 (06) : 1413 - 1422
[9] Design of Hybrid Memristor-MOS XOR and XNOR Logic Gates
Xu, Xiaoyan
Cui, Xiaole
Luo, Mengying
Lin, Qiujun
Luo, Yichi
Zhou, Yufeng
2017 INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2017,
[10] Design of Graphene-Based Plasmonic XNOR/XOR Logic Gates
Zhou Liqiang
Zhang Jie
Ding Jian
Chen Weiwei
ACTA OPTICA SINICA, 2018, 38 (02)

← 1 2 3 4 5 →