Fractional-N phase-locked loop for split and direct automatic frequency control in A-GPS

被引:1
作者
Park, Chester Sungchung [1 ]
Park, Sungkyung [2 ]
机构
[1] Konkuk Univ, Dept Elect Engn, Seoul, South Korea
[2] Pusan Natl Univ, Dept Elect Engn, Busan, South Korea
关键词
Fractional-N; phase-locked loop (PLL); direct automatic frequency control (AFC); split AFC; ultra-high resolution; A-GPS; FAST AFC TECHNIQUE; SYNTHESIZER;
D O I
10.1080/00207217.2018.1426125
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A low-power mixed-signal phase-locked loop (PLL) is modelled and designed for the DigRF interface between the RF chip and the modem chip. An assisted-GPS or A-GPS multi-standard system includes the DigRF interface and uses the split automatic frequency control (AFC) technique. The PLL circuitry uses the direct AFC technique and is based on the fractional-N architecture using a digital delta-sigma modulator along with a digital counter, fulfilling simple ultra-high-resolution AFC with robust digital circuitry and its timing. Relative to the output frequency, the measured AFC resolution or accuracy is <5 parts per billion (ppb) or on the order of a Hertz. The cycle-to-cycle rms jitter is <6ps and the typical settling time is <30s. A spur reduction technique is adopted and implemented as well, demonstrating spur reduction without employing dithering. The proposed PLL includes a low-leakage phase-frequency detector, a low-drop-out regulator, power-on-reset circuitry and precharge circuitry. The PLL is implemented in a 90-nm CMOS process technology with 1.2V single supply. The overall PLL draws about 1.1mA from the supply.
引用
收藏
页码:1200 / 1216
页数:17
相关论文
共 13 条
[1]  
Borkowski MJ, 2006, IEEE INT SYMP CIRC S, P3770
[2]   A 723-MHz 17.2-mW CMOS programmable counter [J].
Chang, HH ;
Wu, JC .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (10) :1572-1575
[3]   Optimized reduction of spur tones in fractional frequency synthesizers [J].
Gonzalez-Diaz, Victor R. ;
Garcia-Andrade, Miguel A. ;
Espinosa, Guillermo F., V ;
Maloberti, Franco .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2010, 65 (02) :245-251
[4]   Speed optimization of edge-triggered CMOS circuits for Gigahertz single-phase clocks [J].
Huang, QT ;
Rogenmoser, R .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (03) :456-465
[5]  
Hwang MW, 2005, IEEE RAD FREQ INTEGR, P679
[6]   A Σ-Δ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications [J].
Lee, HI ;
Cho, JK ;
Lee, KS ;
Hwang, IC ;
Ahn, TW ;
Nah, KS ;
Park, BH .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (07) :1164-1169
[7]  
Lee KS, 2008, IEEE RAD FREQ INTEGR, P267
[8]   Low-jitter process-independent DLL and PLL based on self-biased techniques [J].
Maneatis, JG .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (11) :1723-1732
[9]   A Fractional-N PLL with Dual-Mode Detector and Counter [J].
Park, Fitzgerald Sungkyung ;
Klemmer, Nikolaus .
IEICE TRANSACTIONS ON ELECTRONICS, 2012, E95C (12) :1887-1890
[10]   A 1.9-3.8 GHz ΔΣ Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency [J].
Shin, Jaewook ;
Shin, Hyunchol .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2012, 47 (03) :665-675