Fully Integrated PVT Detection and Impedance Self-Calibration System Design

The paper presents a fully integrated PVT variation detection and on-die resistance calibration system for high-speed applications. The proposed system separately measures and compensates the MOS device resistance deviation due to process, voltage and temperature variation. Temperature detection is performed in a range of -40 degrees C to 125 degrees C independently from supply voltage variations. Logic block of mixed-signal system automatically starts MOS resistance calibration process when PVT variation is detected. The design is implemented in 28nm CMOS process. The presented compensation method can be used in the I/O circuits of such standards as DDR (Double Data Rate), USB (Universal Serial Bus), PCI (Peripheral Component Interconnect), etc.