Statistical modeling for postcycling data retention of split-gate flash memories

被引:6
|
作者
Hu, LC [1 ]
Kang, AC
Shih, JR
Lin, YF
Wu, K
King, YC
机构
[1] Natl Tsing Hua Univ, Dept Elect Engn, Semicond Technol Applicat Res Grp, Hsinchu 300, Taiwan
[2] Taiwan Semicond Mfg Co, Hsinchu 300, Taiwan
关键词
lifetime model; low-temperature data retention (LTDR); program/erase (P/E) cycling; reliability; split-gate Flash memory; stress-induced leakage current;
D O I
10.1109/TDMR.2006.870354
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In developing an accurate lifetime-prediction model for postcycling data-retention failure rate of split-gate Flash memories, a floating-gate potential extraction method from the measured bit-cell-current data is proposed. Stress-induced leakage current through the coupling oxide caused by the source-side channel hot electron injection during program operation is the major cause for postcycling data-retention failure bits. Considering charge conservation and trap-assist-tunneling leakage current, the charge-gain behavior under low-temperature bake is modeled and the failure rate under various measured conditions can be predicted precisely. We have found that data-retention lifetime decreases as program/erase (P/E) cycling increases, while failing bits increase with numbers of P/E cycling.
引用
收藏
页码:60 / 66
页数:7
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