A parallel camera image signal processor for SIMD architecture

被引：1
作者：
Choi, Seung-Hyun [1 ]
Cho, Junguk [2 ]
Tai, Yong-Min [2 ]
Lee, Seong-Won [1 ]
机构：
[1] Kwangwoon Univ, Dept Comp Engn, 20 Kwangwoon Ro, Seoul, South Korea
[2] Samsung Elect Co LTD, DMC R&D Ctr, 129 Samsung Ro, Suwon, Gyeonggi Do, South Korea
来源：
EURASIP JOURNAL ON IMAGE AND VIDEO PROCESSING | 2016年
关键词：
CMOS image sensor; Image signal processor; Reconfigurable processor; Parallel processing optimization; COLOR; DEMOSAICKING;
D O I：
10.1186/s13640-016-0137-2
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An image signal processor (ISP) for a camera image sensor consists of many complicated functions; in this paper, a full chain of the ISP functions for smart devices is presented. Each function in the proposed ISP full chain is designed to handle high-quality images. Every function in the chain is fully converted to a fixed-point arithmetic, and a special function is not used for easy porting to a Samsung Reconfigurable Processor (SRP). Several parallelizing optimization techniques are applied to the proposed ISP full chain for real-time operation on a given 600-MHz reconfigurable processor. To verify the performance of the proposed ISP full chain, a series of tests was performed, and all of the measured values satisfy the quality and performance requirements.
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页数：14
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