Fast FPGA-based pipelined digit-serial/parallel multipliers

被引：0

作者：

Valls, J ^{[1
]}

Sansaloni, T ^{[1
]}

Peiró, MM ^{[1
]}

Boemo, E ^{[1
]}

机构：

[1] Univ Politecn Valencia, Dept Ingn Elect, E-46071 Valencia, Spain

来源：

ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper fast pipelined digit-serial/parallel multipliers are proposed. The conventional digit-serial/parallel multipliers and their pipelined versions are presented. Every structure has been implemented on FPGA and the results are given. These results have been analysed and it is detected that the pipelined ones do not have the throughput improvement expected because of a logic depth increment. As a consequence, a new structure based on the fast serial/parallel multiplier proposed in [1] has been developed. The new multipliers designed achieve better performance than the previous ones: their throughput is higher than it in the pipelined serial/parallel multipliers with nearly the same cost in area.

引用

页码：482 / 485

页数：4

共 9 条

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