A study on signature analyzer for design for test (DFT)

被引：0

作者：

bin A'ain, A ^{[1
]}

Lim, CT ^{[1
]}

Ng ^{[1
]}

Hong, K ^{[1
]}

Kwang, S ^{[1
]}

Yew, LE ^{[1
]}

机构：

[1] Univ Teknol Malaysia, Fac Elect Engn, Dept Elect, Skudai 81310, Johor, Malaysia

来源：

2004 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS | 2004年

关键词：

LFSR; PRBS; BIST; ATPG;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper takes a look at the use of linear feedback shift registers (LFSR's) as test pattern generators (TPG's) and signature analyzers for built-in self-test (BIST). We also propose a method to generate pseudorandom test patterns. The proposed method can generate longer sequences of the same set of test patterns.

引用

页码：138 / 142

页数：5

共 8 条

[1]

Chen CA, 1995, PROCEEDINGS - INTERNATIONAL TEST CONFERENCE 1995, P814, DOI 10.1109/TEST.1995.529913

[2]

DUFAZA C, 1993, DES AUT 1993 EUR EV, P211

[3]

FLORES P, 1999, P 1999 IEEE INT S CI, V1, P114

[4]

Hamzaoglu I., 2000, Proceedings 18th IEEE VLSI Test Symposium, P369, DOI 10.1109/VTEST.2000.843867

[5] Multiple test set generation method for LFSR-Based BIST [J].

Shi, YH ;

Zhe, Z .

ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2003, :863-868

[6]

VASUDEVAN B, 1993, 11TH IEEE VLSI TEST, P201

[7] HYBRID DESIGNS GENERATING MAXIMUM-LENGTH SEQUENCES [J].

WANG, LT ;

MCCLUSKEY, EJ .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1988, 7 (01) :91-99

[8] Accelerated test pattern generators for mixed-mode BIST environments [J].

Wang, WL ;

Lee, KJ .

PROCEEDINGS OF THE NINTH ASIAN TEST SYMPOSIUM (ATS 2000), 2000, :368-373

← 1 →