Area-Efficient High-Speed Hybrid 1-bit Full Adder Circuit Using Modified XNOR Gate

被引：0

作者：

Kadu, Chaitali P. ^{[1
]}

Sharma, Manish ^{[1
]}

机构：

[1] DY Patil Coll Engn, Dept Elect & Telecommun, Pune, Maharashtra, India

来源：

2017 IEEE INTERNATIONAL CONFERENCE ON INFORMATION, COMMUNICATION, INSTRUMENTATION AND CONTROL (ICICIC) | 2017年

关键词：

Hybrid design; CMOS; CPL; Transmission gate; CMOS; LOGIC;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A hybrid 1-bit full adder design is presented here using modified 3T-XNOR gate to improve the area and speed performance. The design is implemented for 1-bit full adder and then is scaled to 32-bit adder. Combination of CMOS and transmission gate logic is used to enhance the performance in terms of area, delay and power. The performance of the proposed design is evaluated through the simulation analysis in 90-nm technology with 1.2v supply voltage. The effect of scaling on the overall performance is also analyzed through the performance evaluation of 1-bit and 32-bit adder. The performance of proposed design is also compared with conventional design to verify the effectiveness in terms of area, power, delay.

引用

页数：5

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