Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS With Random Element Mismatch

被引:34
作者
Fredenburg, Jeffrey A. [1 ]
Flynn, Michael P. [1 ]
机构
[1] Univ Michigan, Dept Elect Engn & Comp Sci, Ann Arbor, MI 48109 USA
基金
美国国家科学基金会; 美国安德鲁·梅隆基金会;
关键词
Analog-digital conversion; analog integrated circuits; mismatch; successive approximation registers; yield; A/D CONVERTER;
D O I
10.1109/TCSI.2011.2177006
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Mismatch motivates many of the design decisions for binary weighted, ratiometric converters, such as successive approximation (SAR) analog-to-digital converters (ADC), but the statistical relationship between mismatch and signal-to-noise-plus-distortion ratio (SNDR) has not been precisely quantified. In this paper, we analyze the effects of capacitor mismatch in a binary weighted, charge redistribution SAR ADC and derive a new analytic expression relating capacitor mismatch and the effective-number-of-bits (ENOB). We then explore the statistics of this new expression and develop a model that accurately predicts yield in terms of ENOB. Finally, the major results of this paper are generalized into a simple and compact design equation that relates resolution, mismatch, and ENOB to yield for all binary weighted, ratiometric converters. The expressions derived in this paper offer practical insight into the relationship between mismatch and performance for all binary, weighted ratiometric converters with these results validated through numerical simulations.
引用
收藏
页码:1396 / 1408
页数:13
相关论文
共 24 条
[1]  
Cong YG, 2002, 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, PROCEEDINGS, P149
[2]   Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays [J].
Cong, YH ;
Geiger, RL .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2000, 47 (07) :585-595
[3]  
Davies R. B., 2018, J. Royal Stat. Soc. Series C: Appl. Stat, V29, P323, DOI 10.2307/2346911
[4]   Reducing the effects of component mismatch by using relative size information [J].
Gregoire, B. Robert ;
Moon, Un-Ku .
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, :512-515
[5]  
Gubener J.A., 2006, Probability and Random Processes for Electrical and Computer Engineers
[6]  
Kester W., 2005, DATA CONVERSION HDB
[7]  
Kosunen M, 2003, PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, P969
[8]   NONLINEARITY ANALYSIS OF RESISTOR STRING A-D CONVERTERS [J].
KUBOKI, S ;
KATO, K ;
MIYAKAWA, N ;
MATSUBARA, K .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1982, 29 (06) :383-390
[9]   CHARACTERIZATION AND MODELING OF MISMATCH IN MOS-TRANSISTORS FOR PRECISION ANALOG DESIGN [J].
LAKSHMIKUMAR, KR ;
HADAWAY, RA ;
COPELAND, MA .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (06) :1057-1066
[10]   Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators [J].
Lee, Seung-Chul ;
Chiu, Yun .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2011, 58 (04) :690-698