Semianalytical Modeling of Short-Channel Effects in Lightly Doped Silicon Trigate MOSFETs

被引:60
作者
Tsormpatzoglou, Andreas [1 ]
Dimitriadis, Charalabos A. [1 ]
Clerc, Raphael [2 ]
Pananakakis, G. [2 ]
Ghibaudo, Gerard [2 ]
机构
[1] Aristotle Univ Thessaloniki, Dept Phys, Thessaloniki 54124, Greece
[2] INPG, Minatec, IMEP Lab, F-38054 Grenoble 9, France
关键词
Analytical potential distribution; corner effect; short-channel effects (SCEs); silicon trigate (TG) MOSFETs;
D O I
10.1109/TED.2008.2003096
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A simple analytical expression of the 3-D potential distribution along the channel of lightly doped silicon trigate MOSFETs in weak inversion is derived, based on a perimeter-weighted approach of symmetric and asymmetric double-gate MOSFETs. The analytical solution is compared with the numerical solution of the 3-D Poisson's equation in the cases where the ratios of channel length/silicon thickness and channel length/channel width are >= 2. Good agreement is achieved at different positions within the channel. The perimeter-weighted approach fails at the corner regions of the silicon body; however, by using corner rounding and undoped channel to avoid corner effects in simulations, the agreement between model and simulation results is improved. By using the extra potential induced in the silicon film due to short-channel effects, the subthreshold drain current is determined in a semianalytical way, from which the subthreshold slope, the drain-induced barrier lowering, and the threshold voltage are extracted.
引用
收藏
页码:2623 / 2631
页数:9
相关论文
共 31 条
[1]  
[Anonymous], INT TECHNOLOGY ROADM
[2]   A simple model for threshold voltage of surrounding-gate MOSFET's [J].
Auth, CP ;
Plummer, JD .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (11) :2381-2383
[3]   Multiple-gate SOI MOSFETs [J].
Colinge, JP .
SOLID-STATE ELECTRONICS, 2004, 48 (06) :897-905
[4]   Shift and ratio method revisited: extraction of the fin width in multi-gate devices [J].
Collaert, N ;
Dixit, A ;
Anil, KG ;
Rooyackers, R ;
Veloso, A ;
De Meyer, K .
SOLID-STATE ELECTRONICS, 2005, 49 (05) :763-768
[5]   High performance fully-depleted tri-gate CMOS transistors [J].
Doyle, BS ;
Datta, S ;
Doczy, M ;
Hareland, S ;
Jin, B ;
Kavalieros, J ;
Linton, T ;
Murthy, A ;
Rios, R ;
Chau, R .
IEEE ELECTRON DEVICE LETTERS, 2003, 24 (04) :263-265
[6]   A 3-D analytical physically based model for the subthreshold swing in undoped trigate FinFETs [J].
El Hamid, Hamdy Abd ;
Guitart, Jaume Roig ;
Kilchytska, Valeria ;
Flandre, Denis ;
Iniguez, Benjamin .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (09) :2487-2496
[7]  
FADLALLAH M, 2000, P 7 INT C EL CIRC SY, V2, P940
[8]   Physical insights on nanoscale multi-gate CMOS design [J].
Fossum, Jerry G. .
SOLID-STATE ELECTRONICS, 2007, 51 (02) :188-194
[9]  
Frank D. J., 1992, International Electron Devices Meeting 1992. Technical Digest (Cat. No.92CH3211-0), P553, DOI 10.1109/IEDM.1992.307422
[10]   Generalized scale length for two-dimensional effects in MOSFET's [J].
Frank, DJ ;
Taur, Y ;
Wong, HSP .
IEEE ELECTRON DEVICE LETTERS, 1998, 19 (10) :385-387