Low electrical resistance silicon through vias: Technology and characterization

System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new architectures, which combine disparate technologies. In particular, when several die have to be connected in a small package, stacking would appear to be the best solution. However, this 3D packaging approach has to satisfy the constraints of high interconnection density and high data throughput in conjunction with good signal integrity, and reliability while maintaining a low cost. Today, several different approaches have been developed in order to perform 3D packaging. These include technologies like SiP (System in Package), SoC (System on Chip) or SoP (System On Package) [1]. A new concept for heterogeneous integration has been developed by CEA-LETI and is called SoW (System On Wafer) [2]. In this paper, the System on Wafer concept (SoW) will be presented. In order to perform heterogeneous integration by using the SoW, a technological toolbox is required. This toolbox. will be presented with a focus on the silicon through vias technology (STV). Then, the complete technology for the STV will be presented. A specific study concerning insulation conformity into the silicon through vias has been led and the results that will be presented. Finally, electrical tests results will be shown for different vias geometries.