A bridging fault model where undetectable faults imply logic redundancy

被引:0
|
作者
Pomeranz, Irith [1 ]
Reddy, Sudhakar M. [2 ]
机构
[1] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA
[2] Univ Iowa, Dept Elect & Comp Engn, Iowa City, IA 52242 USA
来源
2008 DESIGN, AUTOMATION AND TEST IN EUROPE, VOLS 1-3 | 2008年
关键词
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthesis of the circuit. The stuck-at fault model is robust, but other fault models such as certain bridging fault models are not. A robust fault model provides a mechanism to synthesize circuits in which all the target faults are detectable and 100% fault coverage is achievable. The ability to achieve 100% fault coverage, or understand why it is not achievable, is important since the requirement to achieve high test quality translates into a requirement to achieve complete fault coverage for target faults, regardless of the metrics used to measure test quality. We discuss a robust bridging fault model and its use as part of a test generation process for a non-robust bridging fault model (a non-robust bridging fault model may have to be used in order to capture the behavior of bridging defects). We also present experimental results related to the robust bridging fault model.
引用
收藏
页码:1008 / +
页数:2
相关论文
共 50 条
  • [1] Robust Fault Models Where Undetectable Faults Imply Logic Redundancy
    Pomeranz, Irith
    Reddy, Sudhakar M.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, 18 (08) : 1230 - 1234
  • [2] STUCK-AT FAULT-TESTS IN THE PRESENCE OF UNDETECTABLE BRIDGING FAULTS
    YAMADA, T
    NANYA, T
    IEEE TRANSACTIONS ON COMPUTERS, 1984, 33 (08) : 758 - 761
  • [3] On Undetectable Faults and Fault Diagnosis
    Pomeranz, Irith
    Reddy, Sudhakar M.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2010, 29 (11) : 1832 - 1837
  • [4] Redundancy Does Not Imply Fault Tolerance: Analysis of Distributed Storage Reactions to File-System Faults
    Ganesan, Aishwarya
    Alagappan, Ramnatthan
    Arpaci-Dusseau, Andrea C.
    Arpaci-Dusseau, Remzi H.
    ACM TRANSACTIONS ON STORAGE, 2017, 13 (03)
  • [5] Removal of redundancy in combinational circuits under classification of undetectable faults
    Kajihara, Seiji
    Kinoshita, Kozo
    Shiba, Haruko
    Systems and Computers in Japan, 1993, 24 (07): : 31 - 40
  • [6] ANALYTICAL APPROACH OF UNDETECTABLE BRIDGING FAULTS IN COMBINATIONAL CIRCUITS
    Bucur, I. I.
    UNIVERSITY POLITEHNICA OF BUCHAREST SCIENTIFIC BULLETIN SERIES C-ELECTRICAL ENGINEERING AND COMPUTER SCIENCE, 2006, 68 (03): : 63 - 74
  • [7] A parameterizable fault simulator for bridging faults
    Engelke, P
    Becker, B
    Keim, M
    IEEE EUROPEAN TEST WORKSHOP, PROCEEDINGS, 2000, : 63 - 68
  • [8] A Bridging Fault Model for Line Coverage in the Presence of Undetected Transition Faults
    Pomeranz, Irith
    PROCEEDINGS OF THE 2017 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2017, : 938 - 941
  • [9] Efficient double fault diagnosis for CMOS logic circuits with a specific application to generic bridging faults
    Kao, HC
    Tsai, MF
    Huang, SY
    Wu, CW
    Chang, WF
    Lu, SK
    JOURNAL OF INFORMATION SCIENCE AND ENGINEERING, 2003, 19 (04) : 571 - 587
  • [10] Diagnosis of Logic-to-chain Bridging Faults
    Liu, Wei-Chih
    Tsai, Wei-Lin
    Lin, Hsiu-Ting
    Li, James Chien-Mo
    2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2008, : 1051 - 1051