Comparator Metastability in the Presence of Noise

被引:21
作者
Figueiredo, Pedro M. [1 ]
机构
[1] Synopsys Inc, P-2740267 Oporto, Portugal
关键词
Analog-digital conversion; comparator; metastability; sense amplifier; stochastic differential equation; thermal noise; PIPELINE ADC; HIGH-SPEED; CMOS; GS/S; REDUCTION; CONVERTER; NYQUIST; CHANNEL; 6-B;
D O I
10.1109/TCSI.2012.2221195
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Metastability is the inability of a latched comparator to reach a decision in the available amount of time. Existing analyses of metastability disregard noise, treating it as a deterministic phenomenon that inevitably happens every-time the input voltage, upsilon(Idiff), falls in a certain interval around 0, and which is restricted to the aforementioned interval. Also, according to the conventional analysis, the decision takes an infinite amount of time if upsilon(Idiff) = 0 This work analyzes metastability in the presence of noise, showing it is actually a random phenomenon whose probability of occurrence is derived. It is concluded that there is no input value for which metastability inevitably occurs (not even upsilon(Idiff) = 0), and that there may be a significant probability of metastability at input voltage values much larger than those predicted by conventional analysis. All the theoretical results are in agreement with extensive HSPICE transient noise simulations.
引用
收藏
页码:1286 / 1299
页数:14
相关论文
共 65 条
[1]  
[Anonymous], 2011, HSPICE US GUID ADV A
[2]  
[Anonymous], 2009, STOCHASTIC METHODS
[3]  
[Anonymous], 2010, OPERATION MODELING M
[4]  
[Anonymous], P S VLSI CIRC JUN
[5]  
[Anonymous], CMOS MEMORY CIRCUITS
[6]   Dynamic characterisation of high-speed latching comparators [J].
Boni, A ;
Chiorboli, G ;
Morandi, C .
ELECTRONICS LETTERS, 2000, 36 (05) :402-404
[7]  
Carlson A. B., 2009, Communication Systems
[8]   A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS [J].
Chen, Shuo-Wei Michael ;
Brodersen, Robert W. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (12) :2669-2680
[9]   Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC [J].
Chio, U-Fat ;
Wei, He-Gong ;
Zhu, Yan ;
Sin, Sai-Weng ;
U, Seng-Pan ;
Martins, R. P. ;
Maloberti, Franco .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2010, 57 (08) :607-611
[10]   A 550-μW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction [J].
Cho, Sang-Hyun ;
Lee, Chang-Kyo ;
Kwon, Jong-Kee ;
Ryu, Seung-Tak .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (08) :1881-1892