A low-power embedded RISC microprocessor with an integrated DSP for mobile applications

被引：0

作者：

Yamada, T ^{[1
]}

Ishikawa, M

Ogata, Y

Tsunoda, T

Irita, T

Tamaki, S

Nishiyama, K

Kamei, T

Tatezawa, K

Arakawa, F

Nakazawa, T

Hattori, T

Uchiyama, K

机构：

[1] Hitachi Ltd, Cent Res Lab, Kokubunji, Tokyo 1858601, Japan

[2] Hitachi Ltd, Semicond & Integrated Circuits, Kodaira, Tokyo 1878588, Japan

[3] Hitachi ULSI Syst Co Ltd, Kodaira, Tokyo 1878522, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2002年 / E85C卷 / 02期

关键词：

embedded processor; low-power; RISC; DSP; MAC;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 32-bit embedded RISC microprocessor core integrating a DSP has been developed using a 0.18-mum five-layer-metal CMOS technology. The integrated DSP has a single-MAC and exploits CPU resources to reduce hardware. The DSP occupies only 0.5 mm(2). The processor core includes a large on-chip 128 kB SRAM called LT-memory. A large capacity on-chip memory decreases the amount of traffic with an external memory. And it is effective for low-power and high-performance operation. To realize low-power dissipation for the U-memory access, the active ratio of U-memory's access is reduced. The critical path is a load path from the U-memory, and we optimized the path through the whole chip. The chip achieves 0.79 mA/MHz executing Dhrystone 1.1 at 108 MHz, which is suitable for mobile applications.

引用

页码：253 / 262

页数：10