Margin and Energy Dissipation of Adiabatic Quantum-Flux-Parametron Logic at Finite Temperature

We optimized the circuit parameters of a low-power adiabatic quantum-flux-parametron (AQFP) gate in terms of both bit energy and bias margin and confirmed that the bit energy of the optimized gate with a rise time of 200 ps can be decreased to 6% of I-c Phi(0), where I-c is the critical current of the Josephson junctions and Phi(0) is the single flux quantum. In addition, we investigated the effect of thermal noise on the operation of the optimized AQFP gate. The bias margins and bit error rate of the AQFP gate were examined at finite temperature through circuit simulations, in which the thermal noise was taken into account using the Monte Carlo method. The bias margin of the AQFP gate with bias margins of +/- 26% at zero temperature shrunk to +/- 19.4% at 4.2 K, but is still large enough for circuit applications.