A process-scalable low-power charge-domain 13-bit pipeline ADC

被引：24

作者：

Anthony, Michael ^{[1
]}

Kohler, Edward ^{[1
]}

Kurtze, Jeffrey ^{[1
]}

Kushner, Lawrence ^{[1
]}

Sollner, Gerhard ^{[1
]}

机构：

[1] Kenet Inc, Woburn, MA USA

来源：

2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2008年

关键词：

D O I：

10.1109/VLSIC.2008.4586015

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 13-bit ADC is implemented using a novel charge-domain architecture. Enhanced bucket-brigade circuitry and a tapered charge pipeline provide precision charge-domain operation in a standard CMOS process, while eliminating the need for signal-path op-amps. The prototype ADC, implemented in 0.18 mu m CMOS, provides 10.65 ENOB at 250 MS/s while consuming only 140 mW, yielding an exceptionally low FoM of 0.28 pJ/conversion-step. Simulations indicate that the architecture and circuitry are well suited to scaling below 90nm.

引用

页码：222 / 223

页数：2

共 6 条

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