Methodology for low power design of on-line testers for digital circuits

This work is concerned with the development of an algorithm for lowering the power consumption of the tester used in digital circuits with on-line testing (OLT) capability. The proposed scheme is generic and flexible in terms of tradeoffs regarding fault coverage and detection latency versus power and area overheads. Most of the works presented in the literature on OLT have emphasised on minimising area overhead and maintaining high fault coverage. However, power, which was mainly a concern for handheld devices, is now a first order impact factor for deep sub-micron designs. Its increased importance for OLT can be realised from the fact that the tester is executed concurrently with the circuit. The proposed technique can handle generic digital circuits with cell count as high as 15,000 and having the order of 2(500) states. Results for design of on-line fault detectors for various ISCAS89 benchmark circuits are provided. The results illustrate that with marginal impact on performance in terms of coverage and latency, the proposed technique can lower the power and area consumption significantly, compared to traditional approaches.