FPGA Implementation of a Novel Dual - BRAM Processor Architecture

Targeting the continuous demand for processing capabilities, field programmable gate arrays (FPGA) offer a facile platform for processor development. FPGAs answer the need for rapid processor prototyping and testing, while also providing hardware solutions for software engineers. In this context, this work proposes a novel high-speed processor architecture, developed around the traditional Harvard architecture with pipelining. The novelty of this work consists in having two block RAM (BRAM) modules implement the data memory, enabling to simultaneously read and write the instruction data and results respectively. Consequently, every pipeline microinstruction is executed in precisely one clock cycle. Besides the pipeline, a register in the accumulator and logical unit (ALU) allows the employment of execution results in successive instructions. These contributions operate towards high-speed operation of the processor, with an average of one instruction per clock cycle. The proposed processor architecture was implemented in VHDL, and the design was validated by simulation in Xilinx ISIM, as well as by practical tests carried out on an Artix7 35T and a Kintex Ultrascale+ FPGA respectively.