A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence Checking

被引:0
作者
Malik, Raiyyan [1 ]
Baunthiyal, Shubham [1 ]
Kumar, Puneet [1 ]
Srinath, J. [1 ]
Saurabh, Sneh [1 ]
机构
[1] Indraprastha Inst Informat Technol, Delhi, India
来源
PROCEEDINGS OF THE 2022 IFIP/IEEE 30TH INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC) | 2022年
关键词
Verification; Equivalence Checking; Don't Care; Satisfiability; BIT-VECTORS;
D O I
10.1109/VLSI-SoC54400.2022.9939646
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
X-value combinational equivalence checking (XCEC) is a critical problem in verifying refinement-based logic optimizations and ensuring the correctness of low power design methodologies. The critical challenge in XCEC is to establish equivalence in a dramatically expanded search space. We can modify the traditional SAT-based Boolean combinational equivalence checking (CEC) methods to handle X-valued logic by adding an extra bit. However, the XCEC problem becomes more challenging when the two models are X-value equivalent because it involves considering the entire search space to prove the equivalence. Therefore, as an alternative, we propose to use SMT-based frameworks for XCEC by devising appropriate transformations. The proposed formulation allows the SMT solver to pre-process and simplify the encoded satisfiability problem internally. As a result, the SMT-based framework for XCEC is more efficient than a pure SAT-based XCEC, especially for cases in which the revised model is a valid refinement of the given golden model. We have used Cryptominisat5 to implement SAT-based XCEC and STP (with Cryptominisat5 as an internal SAT solver) to implement SMT-based XCEC. Using ICCAD 2020 benchmark suite, we demonstrate that, on an average SMT-based approach is 2.5 x faster than the SAT-based approach for X-value equivalent cases.
引用
收藏
页数:6
相关论文
共 17 条
  • [1] [Anonymous], 2019, 18012018 IEEE, P1
  • [2] [Anonymous], 2015, 615234 IEEEIEC, P1
  • [3] Barrett Clark, 2011, Computer Aided Verification. Proceedings 23rd International Conference, CAV 2011, P171, DOI 10.1007/978-3-642-22110-1_14
  • [4] Satisfiability modulo theories
    Barrett, Clark
    Sebastiani, Roberto
    Seshia, Sanjit A.
    Tinelli, Cesare
    [J]. Frontiers in Artificial Intelligence and Applications, 2009, 185 (01) : 825 - 885
  • [5] Biere A., 2020, P SAT COMPETITION 20, P51
  • [6] Brummayer R, 2009, LECT NOTES COMPUT SC, V5505, P174, DOI 10.1007/978-3-642-00768-2_16
  • [7] Bruttomesso R, 2010, LECT NOTES COMPUT SC, V6015, P150, DOI 10.1007/978-3-642-12002-2_12
  • [8] Z3: An efficient SMT solver
    de Moura, Leonardo
    Bjorner, Nikolaj
    [J]. TOOLS AND ALGORITHMS FOR THE CONSTRUCTION AND ANALYSIS OF SYSTEMS, 2008, 4963 : 337 - 340
  • [9] An extensible SAT-solver
    Eén, N
    Sörensson, N
    [J]. THEORY AND APPLICATIONS OF SATISFIABILITY TESTING, 2004, 2919 : 502 - 518
  • [10] Ganesh V, 2007, LECT NOTES COMPUT SC, V4590, P519