Common-Mode Voltage Eliminated Three-Level Inverter using a Three-Level Flying-Capacitor Inverter and Cascaded H-Bridge

被引：3
|
作者：
RoshanKumar, P. [1 ]
Rajeevan, P. P. [1 ]
Mathew, K. [1 ]
Gopakumar, K. [1 ]
Leon, Jose I. [2 ]
Franquelo, Leopoldo G. [2 ]
机构：
[1] Indian Inst Sci, Ctr Elec Design & Tech, DESE, Bengaluru 560102, India
[2] Univ Seville, Dept Elect Engn, Seville 41004, Spain
来源：
IEEE INTERNATIONAL CONFERENCE ON POWER ELECTRONICS, DRIVES AND ENERGY SYSTEMS (PEDES 2012) | 2012年
关键词：
Common mode voltage elimination; three level inverter; multi-level inverter; INDUCTION-MOTOR DRIVE; BEARING CURRENTS; SCHEME;
D O I：
10.1109/PEDES.2012.6484276
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper proposes a new 3 level common mode voltage eliminated inverter using an inverter structure formed by cascading a H-Bridge with a three-level flying capacitor inverter. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-Bridge fails, the system can still be operated as a normal 3 level inverter mode at full power. This inverter has many advantages like use of single DC-supply, making it possible for a back to back grid-tied converter application, improved reliability etc.
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页数：6
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