Variation Mitigation Technique in SRAM Cell using Adaptive Body Bias

被引:0
作者
Kushwaha, S. [1 ]
Prasad, S. [1 ]
Islam, A. [1 ]
机构
[1] Deemed Univ, Dept Elect & Commun Engn, Birla Inst Technol, Ranchi, Jharkhand, India
来源
PROCEEDINGS OF THE 2012 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, DEVICES AND INTELLIGENT SYSTEMS (CODLS) | 2012年
关键词
Variability; SRAM; RSNM; RDF; DIBL; WRITE OPERATION; DESIGN; VOLTAGE; NOISE;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
This paper presents a circuit technique for designing a variability aware SRAM cell operable at near threshold region. The architecture of the proposed cell is similar to the standard 6T SRAM cell with the exception that DTMOS is used for the access FETs and DSBB (dynamically swapped body bias) scheme is used for feedback and feed-forward inverters of the cell. In this work, various design metrics of the proposed design are assessed and compared with conventional 6T at iso-device area.
引用
收藏
页码:117 / 120
页数:4
相关论文
共 20 条
[1]  
[Anonymous], 2009, FUNDAMENTALS MODERN, DOI DOI 10.1017/CBO9781139195065
[2]   A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing [J].
Bhavnagarwala, Azeez J. ;
Kosonocky, Stephen ;
Radens, Carl ;
Chan, Yuen ;
Stawiasz, Kevin ;
Srinivasan, Uma ;
Kowalczyk, Steven P. ;
Ziegler, Matthew M. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (04) :946-955
[3]   Implementation of low-voltage static RAM with enhanced data stability and circuit speed [J].
Chung, Yeonbae ;
Song, Seung-Ho .
MICROELECTRONICS JOURNAL, 2009, 40 (06) :944-951
[4]   Variability aware low leakage reliable SRAM cell design technique [J].
Islam, A. ;
Hasan, Mohd .
MICROELECTRONICS RELIABILITY, 2012, 52 (06) :1247-1252
[5]   Leakage Characterization of 10T SRAM Cell [J].
Islam, A. ;
Hasan, M. .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (03) :631-638
[6]   A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell [J].
Islam, A. ;
Hasan, Mohd. .
MICROELECTRONICS RELIABILITY, 2012, 52 (02) :405-411
[7]   Variation resilient subthreshold SRAM cell design technique [J].
Islam, Aminul ;
Hasan, Mohd ;
Arslan, Tughrul .
INTERNATIONAL JOURNAL OF ELECTRONICS, 2012, 99 (09) :1223-1237
[8]  
Joon IK. Chang, 2009, IEEE J SOLID STATE C, V44
[9]   A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode [J].
Kim, Tae-Hyoung ;
Liu, Jason ;
Kim, Chris H. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (06) :1785-1795
[10]  
Komatsu Y, 2005, IEEE CUST INTEGR CIR, P35