A CMOS dual-modulus prescaler based on a new charge sharing free D-flip-flop

被引：10
|
作者：
Yang, SH [1 ]
Lee, CH [1 ]
Cho, KR [1 ]
机构：
[1] Chungbuk Natl Univ, Dept Comp & Commun Engn, Cheongju, South Korea
来源：
14TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS | 2001年
关键词：
flip-flops; prescalers; high-speed circuits; low-power circuits;
D O I：
10.1109/ASIC.2001.954711
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A dual-modulus divide-by-128/129 prescaler has been designed using 0.6-mum CMOS technology. A new charge sharing free dynamic D-flip-flop for high-speed operation and low-power consumption is examined in the circuits. The simulated maximum operating frequency and the current consumption of the prescaler are 1.97-GHz and 7.453 mA at 5-V supply voltage, respectively.
引用
收藏
页码：276 / 280
页数：5
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