Drain bias dependent bias temperature stress instability in a-Si:H TFT

The threshold voltage (V-t) instability of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) is investigated under drain bias dependent bias temperature stress (V-D-BTS). The drain bias reduces the overall gate overdrive stress and leads to a position-dependent V-t-shift (Delta V-t) with maximum Delta V-t at the source-end and minimum Delta V-t at the drain-side of channel. Measured Delta V-t was compared with the calculated Delta V-t using a weighted average of local Delta V-t-shift. The calculated Delta V-t based on weighted average agreed better with the measured data in U-type samples, but a simple linear average over the channel agreed better with the measured data in an I-type sample. This is explained in terms of the fact that the source-side channel width is larger than the drain-side width in a U-type sample which results in more contribution from the source-side to the normalized Delta V-t, A non-uniform V-t profile due to V-D-BTS resulted in a higher drain current in the forward measurement (source/drain are the same as in stress) than in reverse measurement (source/drain are interchanged from stress). This also leads to a different extracted V-t in forward and reverse configurations due to the non-uniform V-t profile along the channel. V-t extracted from the saturation transfer curve varies significantly in different current ranges due to the gate bias dependence of field-effect mobility caused by a large variation of the overdrive voltage along the channel. (C) 2008 Elsevier Ltd. All rights reserved.