FPGA implementation of Digital Down Converter using CORDIC algorithm

被引：5

作者：

Agarwal, Ashok ^{[1
]}

Lakshmi, B. ^{[1
]}

机构：

[1] Natl Inst Technol, Dept Elect & Commun Engn, Warangal 506004, Andhra Pradesh, India

来源：

INTERNATIONAL CONFERENCE ON COMMUNICATION AND ELECTRONICS SYSTEM DESIGN | 2013年 / 8760卷

关键词：

CORDIC; Digital Down Converter; FPGA; CIC filter;

D O I：

10.1117/12.2012307

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In radio receivers, Digital Down Converters (DDC) are used to translate the signal from Intermediate Frequency level to baseband. It also decimates the oversampled signal to a lower sample rate, eliminating the need of a high end digital signal processors. In this paper we have implemented architecture for DDC employing CORDIC algorithm, which down converts an IF signal of 70MHz (3G) to 200 KHz baseband GSM signal, with an SFDR greater than 100dB. The implemented architecture reduces the hardware resource requirements by 15 percent when compared with other architecture available in the literature due to elimination of explicit multipliers and a quadrature phase shifter for mixing.

引用

页数：6

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