A design methodology for low-power MCML ring oscillators

被引：3
作者：
Caruso, Giuseppe [1 ]
Macchiarella, Alessio [1 ]
机构：
[1] Univ Palermo, Dipartimento Ingn Elettr Elettron & Telecomun, Palermo, Italy
来源：
2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3 | 2007年
关键词：
D O I：
10.1109/ECCTD.2007.4529686
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mu m CMOS technology. SPICE simulations demonstrate the effectiveness of the design method.
引用
收藏
页码：675 / 678
页数：4
相关论文
共 8 条
[1]   Design strategies for source coupled logic gates [J].
Alioto, M ;
Palumbo, G .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2003, 50 (05) :640-654
[2]   Impact of on-chip process variations on MCML performance [J].
Bruma, S .
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2003, :135-140
[3]   Design of MOS current mode logic gates - Computing the limits of voltage swing and bias current [J].
Caruso, G .
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, :5637-5640
[4]  
ISMAIL AH, 2004, DESIGN LOW POWER MCM, P2383
[5]  
MUSICER J, ANAL MOS CURRENT MOD
[6]   A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching [J].
Park, CH ;
Kim, O ;
Kim, B .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (05) :777-783
[7]  
Razavi B., 2017, DESIGN ANALOG CMOS I
[8]   A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector [J].
Savoj, J ;
Razavi, B .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (01) :13-21
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