A Novel High-Voltage (> 600 V) LDMOSFET With Buried N-Layer in Partial SOI Technology

被引:26
作者
Hu, Yue [1 ]
Huang, Qijun [1 ]
Wang, Gaofeng [2 ]
Chang, Sheng [1 ]
Wang, Hao [1 ]
机构
[1] Wuhan Univ, Sch Phys & Technol, Wuhan 430072, Peoples R China
[2] Wuhan Univ, Inst Microelect & Informat Technol, Wuhan 430072, Peoples R China
基金
中国国家自然科学基金;
关键词
Breakdown voltage (BV); buried N-type layer (BNL); lateral double-diffused metal-oxide-semiconductor (LDMOS); ON-resistance (R-on); partial silicon-on-insulator (PSOI); DEVICES; TRANSISTOR;
D O I
10.1109/TED.2012.2185498
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with a buried N-type layer (BNL) in partial silicon-on-insulator (PSOI) is introduced to achieve breakdown voltage (BV) above 600 V and reduce ON-resistance (R-on). The BNL induces enhanced voltage into the buried oxide layer, which results in higher BV. The higher doping concentration in the BNL can provide more electrons to support higher current and thus reduce ON-resistance. The proposed LDMOS transistor with a BNL in PSOI (BNL-PSOI) is analyzed and compared with LDMOS transistors with conventional SOI (CSOI), conventional PSOI (CPSOI), and a BNL in SOI (BNL-SOI) by 2-D numerical simulations. The results indicate that the proposed structure can significantly improve BV up to 660 V and reduce ON-resistance by 13.6%-15.5% in comparison to CSOI and CPSOI.
引用
收藏
页码:1131 / 1136
页数:6
相关论文
共 17 条
  • [1] SILICON-ON-INSULATOR DEVICES FOR HIGH-VOLTAGE AND POWER IC APPLICATIONS
    ARNOLD, E
    [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1994, 141 (07) : 1983 - 1988
  • [2] A new partial SOI power device structure with P-type buried layer
    Duan, BX
    Zhang, B
    Li, ZJ
    [J]. SOLID-STATE ELECTRONICS, 2005, 49 (12) : 1965 - 1968
  • [3] New 1200V MOSFET structure on SOI with SIPOS shielding layer
    Funaki, H
    Yamaguchi, Y
    Hirayama, K
    Nakagawa, A
    [J]. ISPSD '98 - PROCEEDINGS OF THE 10TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS, 1998, : 25 - 28
  • [4] Compact Modeling of LDMOS Transistors for Extreme Environment Analog Circuit Design
    Kashyap, Avinash S.
    Mantooth, H. Alan
    Vo, Tuan A.
    Mojarradi, Mohammad
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (06) : 1431 - 1439
  • [5] NEW PHYSICAL INSIGHTS AND MODELS FOR HIGH-VOLTAGE LDMOST IC CAD
    KIM, YS
    FOSSUM, JG
    WILLIAMS, RK
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1991, 38 (07) : 1641 - 1649
  • [6] New high-voltage (> 1200 V) MOSFET with the charge trenches on partial SOI
    Luo, Xiaorong
    Zhang, Bo
    Li, Zhaoji
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (07) : 1756 - 1761
  • [7] A novel 700-V SOI LDMOS with double-sided trench
    Luo, Xiaorong
    Zhang, Bo
    Li, Zhaoji
    Guo, Yufeng
    Tang, Xinwei
    Liu, Yong
    [J]. IEEE ELECTRON DEVICE LETTERS, 2007, 28 (05) : 422 - 424
  • [8] Novel Low-k Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI
    Luo, Xiaorong
    Wang, Yuangang
    Deng, Hao
    Fan, Jie
    Lei, Tianfei
    Liu, Yong
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (02) : 535 - 538
  • [9] Realization of High Voltage (> 700 V) in New SOI Devices With a Compound Buried Layer
    Luo, Xiaorong
    Li, Zhaoji
    Zhang, Bo
    Fu, Daping
    Zhan, Zhan
    Chen, Kaifeng
    Hu, Shengdong
    Zhang, Zhengyuan
    Feng, Zhicheng
    Yan, Bin
    [J]. IEEE ELECTRON DEVICE LETTERS, 2008, 29 (12) : 1395 - 1397
  • [10] High-voltage drain extended MOS transistors for 0.18-μm logic CMOS process
    Mitros, JC
    Tsai, CY
    Shichijo, H
    Kunz, K
    Morton, A
    Goodpaster, D
    Mosher, D
    Efland, TR
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (08) : 1751 - 1755