Design of QCA 4-Bit Even Parity Generator Using Multilayer Structure

As interest in quantum-dot cellular automata (QCA) technology has increased, various logic circuits have been proposed in QCA recently. One of logic circuits, a parity generator produces redundant bits used for error detection and is used when transmitting binary information. Many QCA parity generators are designed by locating an input cell in the middle of circuit to reduce an area of the circuit. In addition, a noise was generated in the simulation results because the signal was not propagated correctly by reducing the distance between wires. In this paper, a 4-bit even parity generator is proposed with considering scalability in QCA. The proposed circuit is performed correct simulation and compared with existing parity generator so that prove our circuit's performance.