A novel high speed Artificial Neural Network-based chaotic True Random Number Generator on Field Programmable Gate Array

被引:45
作者
Alcin, Murat [1 ]
Koyuncu, Ismail [2 ]
Tuna, Murat [3 ]
Varan, Metin [4 ]
Pehlivan, Ihsan [4 ]
机构
[1] Afyon Kocatepe Univ, Fac Technol, Dept Mechatron Engn, TR-03200 Afyon, Turkey
[2] Afyon Kocatepe Univ, Fac Technol, Dept Elect & Elect Engn, Afyon, Turkey
[3] Kirklareli Univ, Tech Sci Vocat Sch, Dept Elect, Kirklareli, Turkey
[4] Sakarya Univ, Fac Technol, Dept Elect Elect Engn, Sakarya, Turkey
关键词
artificial neural networks; chaotic systems; field-programmable gate arrays; true random number generators; VHDL; IMPLEMENTATION; TIME; DESIGN; SYSTEM; REALIZATION; ALGORITHM;
D O I
10.1002/cta.2581
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)-based chaotic true random number generator (TRNG) structure has not been unprecedented in current literature. This paper provides a novel type of high-speed TRNG based on chaos and ANN implemented in a Xilinx field-programmable gate array (FPGA) chip. The paper consists of two main parts. In the first part, chaos analyses of Pehlivan-Uyaroglu_2010 chaotic system (PUCS) have been accomplished to prove that PUCS operates in chaotic regime. So PUCS can be an efficient alternative to the entropy source for classical TRNGs. In the second part, the hardware design of the proposed TRNG has been created using VHDL in Xilinx platform. As a result, the implemented TRNG offers throughput up to 115.794 Mbps. Besides, the generated random numbers have been tested with the FIPS 140-1 and NIST 800.22 test suites. The high quality of generated true random numbers have been confirmed by passing all randomness tests. The results have shown that the proposed system can provide not only high throughput but also high quality random bit sequences for a wide variety of embedded cryptographic applications.
引用
收藏
页码:365 / 378
页数:14
相关论文
共 78 条
[41]  
Li Q, 2012, TEL SIGN PROC TSP 20
[42]   Hyperchaos and horseshoe in a 4D memristive system with a line of equilibria and its implementation [J].
Li, Qingdu ;
Hu, Shiyi ;
Tang, Song ;
Zeng, Guang .
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2014, 42 (11) :1172-1188
[43]   Hardware acceleration of pseudo-random number generation for simulation applications [J].
McCollum, JM ;
Lancaster, JM ;
Bouldin, DW ;
Peterson, GD .
PROCEEDINGS OF THE 35TH SOUTHEASTERN SYMPOSIUM ON SYSTEM THEORY, 2003, :299-303
[44]   A minimum five-component five-term single-nonlinearity chaotic jerk circuit based on a twin-jerk single-op-amp technique [J].
Munmuangsaen, Buncha ;
Srisuchinwong, Banlue .
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2018, 46 (03) :656-670
[45]   Dynamic MAC-based architecture of artificial neural networks suitable for hardware implementation on FPGAs [J].
Nedjah, N. ;
da Silva, R. M. ;
Mourelle, L. M. ;
da Silva, M. V. C. .
NEUROCOMPUTING, 2009, 72 (10-12) :2171-2179
[46]  
Ortega-Zamorano F, 2014, INT EMB SYST IES 201
[47]  
oza S, 2014, SIGN EL SYST ICSES I
[48]  
ozcerit AT, 2016, COMPUT ELECT ENG
[49]  
Ozdemir K, 2008, SIGN PROC COMM APPL
[50]   A new S-box construction method based on the fractional-order chaotic Chen system [J].
Ozkaynak, Fatih ;
Celik, Vedat ;
Ozer, Ahmet Bedri .
SIGNAL IMAGE AND VIDEO PROCESSING, 2017, 11 (04) :659-664