Hardware accelerated search for resource-efficient and secure permutation matrices

被引:0
|
作者
Yalcin, Tolga [1 ]
机构
[1] Food & Agr Univ, Dept Comp Engn, Konya, Turkey
来源
IEICE ELECTRONICS EXPRESS | 2016年 / 13卷 / 21期
关键词
hardware acceleration; FPGA; symmetric cryptography; block cipher; permutation layer;
D O I
10.1587/elex.13.20160352
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Permutation layer is a core component of substitution-permutation network block ciphers. Its design directly affects security and resource usage of the block cipher. It is a challenging problem to find permutation matrices with respect to predefined trade-off targets. In our work, we developed a hardware search engine on Xilinx Virtex-6 FPGA in order to accelerate the search of resource-efficient and secure (maximal branch number) 16 x 16 permutation matrices. Our engine completed the full spectrum search in 129 hours 48 minutes and found non-involutory and involutory permutation matrices with maximal branch number of 5 and minimum Hamming weight (HW) of 74 and 80, respectively. To the best of our knowledge, this is the first time that such a hardware accelerated custom search engine has been built and full spectrum permutation matrix search has been performed.
引用
收藏
页数:6
相关论文
共 50 条
  • [1] Secure and resource-efficient communications for telemedicine systems
    Chen, Hanlin
    Ding, Ding
    Zhang, Lei
    Zhao, Cheng
    Jin, Xin
    COMPUTERS & ELECTRICAL ENGINEERING, 2022, 98
  • [2] A Resource-Efficient Hardware Architecture for Connected Component Analysis
    Klaiber, Michael J.
    Bailey, Donald G.
    Baroud, Yousef O.
    Simon, Sven
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2016, 26 (07) : 1334 - 1349
  • [3] A Resource-Efficient and Side-Channel Secure Hardware Implementation of Ring-LWE Cryptographic Processor
    Liu, Dongsheng
    Zhang, Cong
    Lin, Hui
    Chen, Yuyang
    Zhang, Mingyu
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66 (04) : 1474 - 1483
  • [4] TOWARDS RESOURCE-EFFICIENT AND SECURE FEDERATED MULTIMEDIA RECOMMENDATION
    Li, Guohui
    Ding, Xuanang
    Yuan, Ling
    Zhang, Lu
    Rong, Qian
    2024 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING, ICASSP 2024, 2024, : 5515 - 5519
  • [5] A Resource-Efficient Monitoring Architecture for Hardware Accelerated Self-Adaptive Online Data Stream Compression
    Najmabadi, Seyyed Mandi
    Pandit, Prajwala
    Trung-Hieu Tran
    Simon, Sven
    2017 SIGNAL PROCESSING: ALGORITHMS, ARCHITECTURES, ARRANGEMENTS, AND APPLICATIONS (SPA 2017), 2017, : 222 - 227
  • [6] A Secure, Fast, and Resource-Efficient Serverless Platform with Function REWIND
    Song, Jaehyun
    Kim, Bumsuk
    Kwak, Minwoo
    Lee, Byoungyoung
    Seo, Euiseong
    Jeong, Jinkyu
    PROCEEDINGS OF THE 2024 USENIX ANNUAL TECHNICAL CONFERENCE, ATC 2024, 2024, : 597 - 613
  • [7] HACScale: Hardware-Aware Compound Scaling for Resource-Efficient DNNs
    Kong, Hao
    Liu, Di
    Luo, Xiangzhong
    Liu, Weichen
    Subramaniam, Ravi
    27TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2022, 2022, : 708 - 713
  • [8] Resource-Efficient Hardware Implementation of Perspective Transformation Based on Central Projection
    Li, Zeying
    Wang, Weijiang
    Xue, Chengbo
    Jiang, Rongkun
    ELECTRONICS, 2022, 11 (09)
  • [9] Fast and Resource-Efficient Hardware Implementation of Modified Line Segment Detector
    Zhou, Fuqiang
    Cao, Yu
    Wang, Xinming
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2018, 28 (11) : 3262 - 3273
  • [10] Fast and resource-efficient CNNs for Radar Interference Mitigation on Embedded Hardware
    Hirschmugl, Michael
    Rock, Johanna
    Meissner, Paul
    Pernkopf, Franz
    2022 19TH EUROPEAN RADAR CONFERENCE (EURAD), 2022, : 197 - 200