A 1.5 GHz 90 nm embedded microprocessor core

被引：0

作者：

Ricci, F ^{[1
]}

Clark, LT ^{[1
]}

Beatty, T ^{[1
]}

Yu, W ^{[1
]}

Bashmakov, A ^{[1
]}

Demmons, S ^{[1
]}

Fox, E ^{[1
]}

Miller, J ^{[1
]}

Biyani, M ^{[1
]}

Haigh, J ^{[1
]}

机构：

[1] Intel Corp, Chandler, AZ 85226 USA

来源：

2005 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2005年

关键词：

VLSI; microprocessor; power; embedded and cache;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 90 nm ARM (TM) V5TE compatible microprocessor core intended for high performance and low power embedded applications is described. The core includes an ECC protected 2(nd) level 512 MB cache, high-bandwidth single-cycle L1 cache line fill and evict, and cache coherency. Circuit design for high speed and low power are described, as well as their impact on the micro-architecture. Features to support low standby power modes and embedded test are also described.

引用

页码：12 / 15

页数：4

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