A hardware efficient VLSI architecture for FFT processor in OFDM systems

This paper presents a hardware efficient FFT implementation architecture using a novel data access scheme for OFDM applications. By conversion of digit-reversed to bit-reversed order addressing, continuous flow FFT processing can be achieved using 2 N-word memories by alternation between natural order and bit-reversed order addressing. An in-place multi-bank memory is adopted to accommodate high-speed applications such as wireless multimedia communications. Also the bank index generation is performed using bit-wise XOR operations instead of conventional modulo-r additions. The scheme supports scalable length FFT computation and achieves conflict-free memory access.