A hardware efficient VLSI architecture for FFT processor in OFDM systems

被引：0

作者：

Wu, JM ^{[1
]}

Liu, K ^{[1
]}

Shen, B ^{[1
]}

Min, R ^{[1
]}

机构：

[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China

来源：

2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2 | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a hardware efficient FFT implementation architecture using a novel data access scheme for OFDM applications. By conversion of digit-reversed to bit-reversed order addressing, continuous flow FFT processing can be achieved using 2 N-word memories by alternation between natural order and bit-reversed order addressing. An in-place multi-bank memory is adopted to accommodate high-speed applications such as wireless multimedia communications. Also the bank index generation is performed using bit-wise XOR operations instead of conventional modulo-r additions. The scheme supports scalable length FFT computation and achieves conflict-free memory access.

引用

页码：82 / 85

页数：4

共 10 条

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