Impact of device scaling on deep sub-micron transistor reliability - A study of reliability trends using SRAM

被引：0
|
作者：
White, M [1 ]
Huang, B [1 ]
Qin, J [1 ]
Gur, Z [1 ]
Talmor, M [1 ]
Chen, Y [1 ]
Heidecker, J [1 ]
Nguyen, D [1 ]
Bernstein, J [1 ]
机构：
[1] CALTECH, Jet Prop Lab, Pasadena, CA 91109 USA
来源：
2005 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP, FINAL REPORT | 2005年
关键词：
D O I：
10.1109/IRWS.2005.1609574
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
As microelectronics are scaled in to the deep submicron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes Step-Stress techniques to evaluate memory technologies (0.25um, 0.15um, and 0.13um) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.
引用
收藏
页码：103 / 106
页数：4
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