Frequency Synthesizer With Dual Loop Frequency and Gain Calibration

被引：8

作者：

Jakobsson, Anders ^{[1
]}

Grewing, Christian ^{[1
]}

Serban, Adriana ^{[2
]}

Gong, Shaofang ^{[2
]}

机构：

[1] Huawei Technol Sweden AB, S-16494 Kista, Sweden

[2] Linkoping Univ, Dept Technol & Sci, S-60174 Norrkoping, Sweden

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2013年 / 60卷 / 11期

关键词：

Automatic frequency calibration; automatic gain calibration; bang-bang phase detector; frequency synthesizer; phase-locked loop;

D O I：

10.1109/TCSI.2013.2256191

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 3600-MHz phase-locked loop based frequency synthesizer for UMTS applications has been developed in 0.18 mu m CMOS. It incorporates a VCO frequency and loop-gain calibration technique that allows an integrated VCO frequency tuning range of 28% and a low VCO gain (K-VCO of 30 MHz/V. The loop-gain calibration can compensate for not only variations in VCO gain and divider modulus, but also charge-pump current and loop filter capacitance to an accuracy of 5%. The PLL settles in 150 mu s including frequency and gain calibrations. No switches are used in the loop filter. The output phase noise at 1-MHz offset is -123 dBc/Hz and the integrated phase error (1 kHz-2 MHz) is 1.26 degrees.

引用

页码：2911 / 2919

页数：9

共 15 条

[1] CMOS PLL calibration techniques [J].