Scalable Electrical Compact Modeling for Graphene FET Transistors

被引：92

作者：

Fregonese, Sebastien ^{[1
]}

Magallo, Maura ^{[1
]}

Maneux, Cristell ^{[1
]}

Happy, Henri ^{[2
]}

Zimmer, Thomas ^{[1
]}

机构：

[1] Univ Bordeaux, CNRS, F-33000 Bordeaux, France

[2] Univ Lille 1, Sci & Technol IEMN Lab, F-59650 Villeneuve Dascq, France

来源：

IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2013年 / 12卷 / 04期

关键词：

Circuit; SPICE; compact; electrical; graphene; large signal; model; transistor;

D O I：

10.1109/TNANO.2013.2257832

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new scalable electrical compact model for the Graphene FET devices is proposed. Starting from Thiele's quasi-analytical model, the equations are modified to be fully compatible with SPICE-like circuit simulation. Compared to Meric et al. model, the charge model is improved. This large signal model has been implemented in Verilog-A code and can be used for simulation in a standard circuit design environment such as Cadence or ADS. This model has been verified using different measurements from the literature, and furthermore, its scalability is demonstrated.

引用

页码：539 / 546

页数：8

共 36 条

[1] Electron Transport in Graphene From a Diffusion-Drift Perspective [J].