Design of a high-speed low-power CAM

被引：0

作者：

Gu, CH ^{[1
]}

Zhu, HF ^{[1
]}

Zhou, XF ^{[1
]}

Min, H ^{[1
]}

Zhou, D ^{[1
]}

机构：

[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China

来源：

2005 6th International Conference on ASIC Proceedings, Books 1 and 2 | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A low power Content Addressable Memory is presented in this paper. Two-stage comparison is used to get good performance in TLB and the best low power structure is put forward based on the power model. Lower voltage swing is also applied to reduce the power dissipation. This circuit is implemented in 0.18um IP6M CMOS process. Simulation results indicate that it only consumes 4.59 mu w/bit with the maximum delay of 0.983ns in a 64-entry TLB.

引用

页码：187 / 190

页数：4

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