Hardware Accelerator for Boosting Convolution Computation in Image Classification Applications

被引：0

作者：

Chang, Meng-Chou ^{[1
]}

Pan, Ze-Gang ^{[1
]}

Chen, Jyun-Liang ^{[1
]}

机构：

[1] Natl Changhua Univ Educ, Dept Elect Engn, Changhua 50074, Taiwan

来源：

2017 IEEE 6TH GLOBAL CONFERENCE ON CONSUMER ELECTRONICS (GCCE) | 2017年

关键词：

Convolutional neural network; image classification;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).

引用

页数：2