FROM DESIGN WITH SYSML TO VHDL-AMS SIMULATION

被引：0

作者：

Verries, Jean ^{[1
]}

Paludetto, Mario ^{[1
]}

Sahraoui, Abd-El-Kader ^{[1
]}

机构：

[1] CNRS, LAAS, 7 Ave Colonel Roche, F-31077 Toulouse, France

来源：

EUROPEAN SIMULATION AND MODELLING CONFERENCE 2008 | 2008年

关键词：

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

An approach combining SysML and VHDL-AMS is proposed in this paper. The design is modeled with SysML and then we derive some intuitive rules to obtain the VHDL-AMS model of the lower level blocks built in SysML. The work is at the level of the tentative approach that is being carried out on real industrial application for onboard systems. The paper goes beyond the models issues and carries out the simulation procedure that are available on tools to validate the design for the intended blocks.

引用

页码：115 / +

页数：2

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