Fractional-N PLL with 90° phase shift lock and active switched-capacitor loop filter

被引：0

作者：

Park, J ^{[1
]}

Maloberti, F ^{[1
]}

机构：

[1] Univ Texas, Richardson, TX 75083 USA

来源：

CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a new possibility of fully integrated fractional-N phase locked loop (PLL). The approach uses switched-capacitor fully differential low pass filter (LPT) instead of huge continuous-time filter. The discrete-time operation has the potential to provide a phase noise enhancement (PNE) block, variable gain, to improve noise. The circuit is implemented in 2.8 mm(2) including all capacitors and EA modulator using 0.25 pm CMOS process. The proposed PLL achieves a phase noise of -102 dBc at 600 kHz and spur level of -80 dBc with mid-band frequency. Power dissipation is 30 mW with a 3-V supply.

引用

页码：329 / 332

页数：4