Signal Integrity Issues due to ESD events in High-Speed CMOS Comparator

被引：0

作者：

Nicuta, Ana-Maria ^{[1
]}

Bicleanu, Paul ^{[1
]}

Salceanu, Alexandru ^{[1
]}

机构：

[1] Gheorghe Asachi Tech Univ Iasi, Fac Elect Engn, Iasi, Romania

来源：

2013 8TH INTERNATIONAL SYMPOSIUM ON ADVANCED TOPICS IN ELECTRICAL ENGINEERING (ATEE) | 2013年

关键词：

CMOS comparator; electrostatic discharge; high-speed; signal integrity; PROTECTION CIRCUITS; DESIGN METHODOLOGY;

D O I：

10.1109/ATEE.2013.6563353

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper is mainly focused on analyzing the behavior of the output data of a CMOS latched comparator subjected to the Human Body Model (HBM) Electrostatic Discharge (ESD) test event. The importance of the comparator circuit in the applications of data transmission is illustrated. Several tests using the Cadence IC 5.3 software were carried out in order to investigate the accuracy of the output data signal. The tests were computed for the high and low level of the clock. The malfunction of the comparator structure due to the effects of the electrostatic field is investigated. The functioning of the circuit was improved by adding decoupling capacitors with protective properties.

引用

页数：6

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